Dielectric thin films are used in integrated circuits, for example, to provide insulating layers between different electrically-conductive layers: in MOS technology, for example, such films are used to electrically insulate the polysilicon gates of the MOS transistors from the overlaying metal interconnection lines.
Dielectric thin films are commonly represented by oxide layers doped with boron and phosphorous (known as "Boron-Phosphorous Silicate Glass" or "BPSG"). These layers are deposited by means of the Chemical Vapor Deposition ("CVD") technique.
BPSG films allow the formation of a planar surface over the substrate wherein circuit devices are integrated. To this end, after their deposition, the oxide films undergo a thermal process ("reflow") in furnaces or in Rapid Thermal Annealers ("RTA") at temperatures near their melting point (800-1000.degree. C.) to obtain a planar surface.
The melting-point temperature of such films depends on their doping level, and for a given total impurity concentration (sum of the phosphorous and boron concentrations), decreases for higher boron concentrations.
Some integrated circuits, such as non-volatile memory devices (EPROMs and Flash EPROMs), often require BPSG films with high phosphorous concentrations (typically over 6%), since phosphorous atoms act as gettering centers for high-mobility metal impurity species that may cause a performance degradation of the memory cells (i.e., leakage of charges stored in the floating gates, causing the loss of the stored information). Such a planarization process is difficult to perform for non-volatile semiconductor memory devices such as EPROM and Flash EEPROM. Since to achieve stable BPSG films the total impurity concentration must not exceed a given value, the boron concentration must be low (less than 3%), and the resulting melting-point temperature is too high and not compatible with the new-generation integrated devices. Such a high melting-point temperature prevents an effective planarization of the surface of the BPSG film from being achieved.
EP-A-0280276 discloses an UV erasable nonvolatile semiconductor memory device having an interlayer insulation film between memory elements and an upper metal wiring layer. The interlayer insulation film comprises a thermal oxide film formed on a semiconductor substrate, a phosphorus doped oxide (PSG) film formed on the thermal oxide film, and a boron and phosphorus doped (BPSG) film formed on the PSG film. The PSG film improves the UV transmissive properties of the insulation film. After its deposition, the BPSG film is reflowed by means of a thermal process at 900.degree. C.
Such an interlayer insulation film has two major drawbacks: first, since the PSG film has a melting temperature substantially higher than that of the BPSG film, it does not reflow at 900.degree. C., and thus does not aid in the formation of a highly planar interlayer insulation film. Second, if cleaning of the bottom of the contact windows is carried our by wet etching, such as by means of hydrofluoric acid-based solutions, then the contact windows may be deformed, because the PSG film etch rate is substantially higher than that of the BPSG film.